The present invention relates to a semiconductor device and, more particularly, to a ringing masking device which can resolve a data error due to a ring-back noise in a semiconductor memory device.
Semiconductor devices have been continuously improved both in terms of enhanced operation speed as well as increased integration density. In order to enhance the operation speed of semiconductor devices, a synchronous memory device operating synchronously with a clock given from the outside of a memory chip has been introduced. A double data rate (DDR) synchronous memory device in which two data are inputted or outputted at a single clock period has been suggested for high speed operation.
Presently, in order to realize precise timing for data input/output during high speed operation, a data strobe signal DQS is inputted together with a data signal from a central processing unit or a memory controller outside of the memory device when the data is inputted into the memory device.
The data strobe signal DQS returns to a high impedance state after completion of a postamble, and a ringing may occur before returning to the high impedance state. When the ringing is present after completion of the postamble errors occur as data is latched in synchronization with the rising and falling edges of the erroneous DQS signal corrupted by the ringing. Efforts to solve the problem associated with ringing as discussed above have been made.
FIG. 1 is shows a conventional ring-back noise masking circuit which prevents errors due to the ringing.
Referring to FIG. 1, the ring-back noise mask circuit comprises a DQS buffer unit 10 buffers a data strobe signal DQS to output a buffer signal IDQS, a driver unit 20 outputs the buffer signal IDQS as a driver signal DQSIR according to a control signal, a pulse output unit 30 receives the driver signal DQSIR and outputs a rising pulse DQSRP and a falling pulse DQSFP, and a driver control unit 40 which receives the driver signal DQSIR and outputs a driver control signal DISDSP that disables the driver signal DQSIR.
According to an embodiment of the present invention, a double input buffer that receives data strobe signal pair DQS and DQSB to perform the buffering may be used as the DQS buffer unit 10. Alternatively, a single input buffer that receives the data strobe signal DQS and a reference voltage VREF may also be used, or both the single input buffer and the double input buffer may be used together.
The driver unit 20 outputs the driver signal DQSIR according to the control of the buffer signal IDQS and the control signal DISDSP outputted from the control unit 40. The driver signal DQSIR is outputted as the rising pulse DQSRP and the falling pulse DQSFP through the output unit 30.
Lastly, the control unit 40 comprises a pulse generation unit 42 that receives the driver signal DQSIR and generates a pulse signal DQSP, and a control signal generation unit 46 that receives the pulse signal DQSP and a burst end signal WT24R, applied from the outside, and generates the control signal DISDSP.
The pulse generation unit 42 comprises a delay unit 44 that delays the driver signal DQSIR by a predetermined time, and combines the driver signal DQSIR and the delayed driver signal to generate the pulse signal DQSP. The control signal generation unit 46 comprises a PMOS transistor P1 and NMOS transistor N1, each receiving the burst end signal WT24R as a common gate input, and an NMOS transistor N2 that receives the pulse signal DQSP as a gate input. Also, the control signal generation unit 46 may further comprises a latch unit 48 that latches the outputs of the transistors N1 and N2 and an inverter INV1 that inverts the output of the latch unit 48. The burst end signal is generated according to a counting clock with an internal clock signal in consideration of a burst length BL after an internal write command signal is inputted.
With the above configuration, the control signal DISDSP is enabled to a low level when both the burst end signal WT24R and the pulse signal DQSP become high level.
The driver unit 20 includes a NAND gate ND that receives the control signal DISDSP, and is turned off when the control signal DISDSP is enabled to the low level. Therefore, it is possible to prevent outputting the ringing of the DQS.
FIGS. 2 through 4 show operation waveform diagrams of FIG. 1.
FIG. 2 shows a waveform when the data strobe signal DQS is normally inputted, FIG. 3 shows a waveform when the data strobe signal DQS is inputted in a fast mode, and FIG. 4 shows a waveform when the data strobe signal DQS is inputted in a slow mode.
Referring to FIG. 2, it can be appreciated that when the burst end signal WT24R, which is applied from the outside, is maintained at a high level the control signal DISDSP is enabled to a low level at a rising edge of the pulse signal DQSP generated by the driver signal DQSIR. Therefore, it is possible to prevent the output of the pulse which is generated by the ringing.
However, according to the conventional device, as shown in FIG. 1, inputting the data strobe signal DQS earlier, i.e., in a tDQSSmin condition, does not solve the error associated with the related art.
Referring to FIG. 3, the rising edge of the burst end signal WT24R, which is applied from the outside, is delayed more than the rising edge of the pulse signal DQSP, which is synchronized with the data strobe signal DQS(fast). Therefore, the control signal DISDSP is not enabled immediately at the rising edge of the pulse signal DQSP, but rather enabled at the delayed rising edge of the burst end signal WT24R. Therefore, delay corresponding to tERR is generated, which results in the output of a pulse due to the ringing. In order to solve the above error, a method that shortens the burst end signal WT24R to advance its rising edge before the rising edge of the pulse signal DQSP may be suggested. However, another problem, as shown in FIG. 4 and described below, is still generated.
The error is still generated when the data strobe signal DQS is inputted later, i.e. in a tDQSSmax condition.
Referring to FIG. 4, it can be appreciated that a rising edge of the burst end signal WT24R occurs during a high period of a pulse DQSP, which is synchronized with a third pulse of the data strobe signal DQS(slow), as the data strobe signal DQS(slow) is inputted later. Therefore, when the rising edge of the burst end signal WT24R occurs, a more serious error occurs. That is, the control signal DISDSP is enabled to the low level and the fourth normal pulse cannot be inputted.
In order to prevent such an error, the rising edge of the burst end signal WT24R should occur after the falling edge of the pulse signal DQSP synchronized with the third pulse of the strobe signal DQS(slow). In other words, a margin tMARGIN, as shown in FIG. 4, should be ensured. Another serious problem may occur when advancing the time point of pulse generation of the burst end signal WT24R to prevent the error in the tDQSSmin. That is, a normal signal cannot be outputted, because the control signal DISDSP is enabled in the high period of the third pulse as the margin tMARGIN (which can ensure effective data) is not ensured.